1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof and, more particularly, to a transistor including a semiconductor layer containing germanium.
2. Description of the Related Art
According to the International Technology Roadmap for Semiconductors (ITRS2001), not only alteration of design rule generations but also introduction of new materials and structures will be accelerated after the 65 nm-generation process. One of the causes of such acceleration is that it becomes more difficult to obtain satisfactory drive current than before due to source voltage scaling, deterioration of carrier mobility and the like. In attempt to solve these problems, a proposal has been made of a device in which a new material having a high carrier mobility such as strained silicon or silicon-germanium (SiGe) is introduced into the channel thereof (see J. L. Hoyt and seven others, “Strained Silicon MOSFET Technology”, International Electron Device Meeting (IEDM) 2002, P23–26 for example.)
Silicon-germanium has a higher carrier (hole) mobility than silicon. For this reason, the use of silicon-germanium for the p-channel of a field effect transistor makes it possible to realize a higher-speed operation without relying upon miniaturization.
A heterojunction dynamic threshold MOS transistor has been proposed as the art of enhancing the performance of a transistor having a heterojunction channel containing a silicon-germanium layer (see Japanese Patent Laid-Open Publication No. 2002-314089.)
Also, a proposal has been made of a technique on a high-performance transistor with a strained silicon channel formed by adopting a silicon-germanium layer as a substrate.
Also, a germanium-containing cobalt silicide phase formation technique has been reported such that the value of resistance of a silicide layer can be lowered by simply raising the annealing temperature (see R. A. Donaton and six others, “Co silicide formation on SiGeC/Si and SiGe/Si layers”, Applied Physics letter 70(10), 10 Mar. 1997, P1266–1268.)
Also, a proposal has been made of a source and drain structure raised up by selective epitaxial growth of a silicon layer as a technique of reducing the parasitic resistance of source and drain (see Japanese Patent Publication No. 2964925.)
At present, however, silicon-germanium for use in channels is different from silicon in the reaction temperature causing reaction with cobalt, which is frequently used as a silicide material for forming source and drain electrodes. As a result, the annealing temperature need to be 100–200° C. higher than the conventional annealing temperature (about 600–700° C.) in order to obtain a Co(SiGe) phase having a resistance as low as that of a CoSi2 phase. Accordingly, the process temperature hysteresis becomes undesirably higher, causing impurity diffusion, lattice strain relaxation and the like to occur, which might result in a failure to obtain desired impurity concentration profile and electrical characteristics. On the other hand, a special relaxed silicon-germanium substrate is presently needed in fabricating a transistor employing strained silicon. Since a silicon-germanium layer having a μm-order thickness is present in such a substrate underlying a strained silicon layer as thin as about 20 nm, a problem arises such that the temperature for forming a low-resistant silicide layer also becomes higher.
Further, germanium is a contamination source against the silicon process and, hence, its influence on the device reliability is concerned about. Therefore, device structure and fabrication process contrived to prevent germanium contamination are indispensable for such devices as mentioned above.